1. Field of the Invention
The present invention relates to switching regulators and, more particularly, to a completely isolated synchronous boost DC-to-DC switching regulator.
2. Description of the Related Art
A boost DC-to-DC switching regulator is a device that provides a DC output voltage on an output node that is higher than the DC input voltage on the input node by switching the output of an inductor between ground and a diode connected to the output node. A synchronous boost DC-to-DC switching regulator utilizes a pair of switches, such as an NMOS transistor and a PMOS transistor, to switch between ground and the output node.
FIG. 1 shows a schematic diagram that illustrates a prior-art, synchronous boost DC-to-DC switching regulator 100. As shown in FIG. 1, switching regulator 100 includes an input node NIN that receives a DC input voltage VIN, an input capacitor CIN that has a first plate connected to the input node NIN and a second plate connected to ground, and an inductor L that has a first end connected to the input node NIN, and a second end connected to a switch node NSW.
Switching regulator 100 also includes an NMOS transistor M1 and a PMOS transistor M2. NMOS transistor M1 has a drain connected to the switch node NSW, a source coupled to ground, and a gate connected to receive a first drive signal Ndrive. PMOS transistor M2, in turn, has a drain connected to the switch node NSW, a source connected to an output node NOUT, and a gate connected to receive a second drive signal Pdrive. Further, the p+ drain and source of PMOS transistor M2 are formed in an n− body 110 that is electrically connected to an output voltage VOUT on the output node NOUT.
In addition, switching regulator 100 includes an output capacitor COUT that has a first plate connected to the output node NOUT, and a second plate connected to ground. Further, a load 112 is connected between the output node NOUT and a feedback node NFB, which is coupled to ground via a resistor R1. Examples of loads include one or more resistors (which set a fixed output voltage) and a series of white light emitting diodes (LEDs).
Switching regulator 100 also includes a control circuit 114 that is connected to the gate of transistor M1 to output the first drive signal Ndrive, the gate of transistor M2 to output the second drive signal Pdrive, and the feedback node NFB to receive a feedback voltage VFB. Control circuit 114 can be implemented as a pulse width modulation (PWM) controller, a pulse frequency modulation (PFM) controller, a burst mode controller, or any other means of regulating a voltage using 2 synchronous switches and an inductor and capacitor.
In operation, assuming the output voltage VOUT equals the input voltage VIN, control circuit 114 turns on NMOS transistor M1 and turns off PMOS transistor M2. When transistor M1 turns on, ground is placed on the second end of inductor L which, in turn, causes a current (that changes with time) to flow through inductor L and NMOS transistor M1 to ground.
The current increases at a rate of VIN/L. The voltage at the switch node NSW is equal to the resistance of the NMOS transistor M1 multiplied times the inductor current. The voltage does not increase to VIN. When transistor M1 is on, the voltage on the switch node NSW is low (Rdson*the inductor current).
After this, control circuit 114 turns off NMOS transistor M1 and turns on PMOS transistor M2. Transistor M1 is turned off by either a current limit, duty cycle maximum, or a fixed time if using a fixed on-time PFM type control loop. The current flowing in an inductor cannot change value instantaneously.
As a result, a current flows through PMOS transistor M2 to output capacitor COUT and load 112, where the current charges up the output voltage VOUT on output capacitor COUT to a magnitude that is greater than the magnitude of the input voltage VIN. In addition, since transistor M2 is on, the voltage on the switch node NSW is approximately VOUT.
Following this, control circuit 114 again turns on NMOS transistor M1 and turns off PMOS transistor M2. Transistor M2 is turned off by either a current limit, duty cycle maximum, or a fixed time if using a fixed on-time PFM type control loop. When NMOS transistor M1 turns on, the voltage on switch node NSW again drops to ground (the switch node NSW switches between ground (M1 on) and VOUT (M2 on). When PMOS transistor M2 turns off, output capacitor COUT discharges, thereby providing the current to load 112.
Control circuit 114 then continues, alternating between turning on PMOS transistor M2 and NMOS transistor M1. In addition, control circuit 114 receives the feedback voltage VFB from the feedback node NFB and, in response to the feedback voltage VFB (along with any other additional sensed lines), adjusts the period of time that NMOS and PMOS transistors M1 and M2 are turned on to insure that a substantially constant current is sourced to load 112. (For voltage mode PWM control, only the feedback voltage VFB is needed for regulation. However, for current mode PWM control, both the feedback voltage VFB and a sensed inductor current are needed.)
One drawback of switching regulator 100 is that switching regulator 100 operates poorly (is leaky) when in shutdown mode. Switching regulator 100 has two modes of operation: a shutdown mode where the input voltage VIN is greater than the output voltage VOUT; and a normal mode where the output voltage VOUT is greater than the input voltage VIN.
FIG. 2 shows a cross-sectional view that illustrates prior-art PMOS transistor M2 of switching regulator 100. As shown in FIG. 2, a parasitic PNP bipolar transistor Q1 is formed from transistor M2, where the drain of transistor M2 functions as the emitter, the source of transistor M2 functions as the collector, and the body functions as the base, providing base resistance R2, which is connected to the output voltage VOUT.
As shown in FIG. 2, whenever the voltage on the switch node NSW is a junction drop, e.g., 0.7V, greater than the output voltage VOUT, the emitter-base junction forward biases, which then turns on parasitic PNP bipolar transistor Q1. As a result, a leakage current flows through PMOS transistor M2 when switching regulator 100 enters the shutdown mode (when VIN is greater than VOUT).
In addition to wasting power, the leakage current can also drain a battery when the input node NIN is connected to the battery. Thus, there is a need for a synchronous boost DC-to-DC switching regulator that eliminates the parasitic PNP transistor, and thereby eliminates the leakage current through PMOS transistor M2 when switching regulator 100 enters the shutdown mode (when VIN is greater than VOUT).